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devices can share the EBI lines and be identified by the EBI_CSn line. Each bank can individually be
enabled or disabled in the EBI_CTRL register. The bank separation is 64 MB. Refer to the memory map
of the EFM32G for a more detailed specification on the memory locations available.
14.3.7 WAIT/ARDY.
Some external devices are able to indicate that they are not finished with either write or read operation
by asserting the WAIT / ARDY line. This input signal is used to extend the REn/WEn cycles. The
interpretation of the polarity of this signal can be configured with the ARDYPOL bit in EBI_POLARITY.
E.g. if the ARDYPOL is set to ACTIVELOW, then the REn/WEn cycle is extended while the ARDY line
is kept low. The ARDY functionality is enabled by setting the ARDYEN bit in the EBI_CTRL register. It is
also possible to enable a timeout check, which generates a bus error if the ARDY is not deasserted within
the timeout period. This prevents a system lock up condition in the case that the external device does not
deassert ARDY. The timeout functionality is disabled by setting ARDYTODIS in the EBI_CTRL register.
14.3.8 Control Signal Polarity
It is possible to individually configure the control signals to be active high/low by setting or clearing the
appropriate bits in the EBI_POLARITY register.
14.3.9 Pin Configuration
In order to give the EBI access to the external pins of the EFM32G, the GPIO must be configured
accordingly. The lines must be set to Push-Pull, which is described in detail in the GPIO section.
All the EBI pins are enabled in the EBI_ROUTE register. The EBI_AD, EBI_WEn and EBI_REn pins are
all enabled by the EBIPEN bit, the EBI_CSn pins are enabled by the corresponding CSxPEN bit, the
EBI_ALE pin is enabled by the ALEPEN bit , and the EBI_ARDY pin is enabled by the ARDYPEN bit
of the EBI_ROUTE register.
2011-04-12 - d0001_Rev1.10
139
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